This invention relates to a comparator array with a capacitor network, and it further pertains to an ADC (analog-to-digital converter) with the comparator array.
High-speed voltage comparators have been applied particularly to an ADC for image processing. Inverter chopper comparators, composed of CMOS transistors, are known in the art. This inverter chopper comparator finds many applications in monolithic ADC's that are realized by VLSI process technology for CMOS transistors.
FIG. 20 illustrates the typical configuration of an inverter chopper comparator made up of CMOS transistors. The configuration of first to fourth switches SW1, SW2, SW3, and SW4 is selected from among those, as shown in FIG. 21, namely, a PMOS transfer gate (FIG. 21 (b)), an NMOS transfer gate (FIG. 21 (c)), and a CMOS transfer gate (FIG. 21 (d)). An analog input signal source 1 is connected to one terminal of SW1, and the other terminal of SW1 is connected to one terminal of a first coupling capacitor C1. One terminal of SW2 is connected to a series of reference resistors 4 that divides a potential difference between two reference voltage sources 2 and 3, while the other terminal of SW2 is connected to the same terminal of the first coupling capacitor C1 that SW1 is connected to. The remaining terminal of the first coupling capacitor 1 (i.e., the terminal as not being connected to SW1 or SW2) is connected to the input terminal of a first inverter 6. Second and third inverters are indicated by reference numerals 12 and 13, respectively.
The configuration of the inverters 6, 12, and 13 is selected from among those, shown in FIG. 22, namely a CMOS inverter (FIG. 22 (b)), an E/E inverter (FIG. 22 (c)), and an E/D inverter (FIG. 22 (d)). One terminal of SW3 is connected to the input terminal of the first inverter 6, while the other terminal of SW3 makes connection with the output terminal of the inverter 6. One terminal of a second coupling capacitor C3 is connected to the input terminal of the second inverter 12, and the other terminal of coupling capacitor C3 is connected to the output terminal of the first inverter 6. One terminal of SW4 is connected to the input terminal of the second inverter 12, and the other terminal thereof is connected to the output terminal of the second inverter 12. The output terminal of the second inverter 12 is connected to the input terminal of the third inverter 13.
The operation concerning the above is now described. FIG. 23 is the on/off timing diagram of SW1 to SW4, in which HIGH-level indicates an on-state while LOW-level indicates an off-state.
During the sampling period, SW1, SW3, and SW4 are turned on. Then the analog input signal source 1 is connected to the first coupling capacitor C1. The analog input voltage of Vin from the source 1 is developed at the one terminal of C1. Developed at the other terminal of C1 is the voltage of Va corresponding to operating point A of FIG. 24. Since SW3 is on, both voltages, appeared at the input and output terminals of the first inverter 6, are Va at point A at which the static characteristic curve of the input voltage versus the output voltage intersects the line where the input and output voltages are equal to each other. Since SW4 is likewise on, both voltages, appeared at the input and output terminals of the second inverter 12, are Va.
During the holding period, SW1, SW3, and SW4 are now turned off. This allows for the first coupling capacitor C1 to hold a potential difference, between Vin and Va. From the relation between the electric charge stored and the difference of terminal voltages in a parallel plate capacitor (i.e., the relation of Q=CV), the electric charge Q1, held in the coupling capacitor C1, is: EQU Q1=C1 (Vin-Va) (1)
During the comparison period, SW2 is turned on. Then, a potential difference between the voltage Vb at the input terminal of the first inverter 6 and the reference voltage of Vref is applied across the coupling capacitor C1. SW3 is in off-state, and the input terminal of the first inverter 6 is of a MOS transistor gate. Thus, input impedance of the first inverter 6 is considerably high enough to assume that the inflow and outflow of a current can practically be disregarded. Therefore, the electric charge, stored at the input terminal of the first inverter 6, has been maintained since the holding period. This makes the following formula hold. EQU Q1=C1 (Vref-Vb) (2)
To find Vb, the formula (2) is substituted by the formula (1) to eliminate Q1. EQU Vb=Vref-Vin+Va (3)
The formula (3) proves that Vb (i.e., the voltage at the input terminal of the first inverter 6) changes from Va by (Vref-Vin) (see FIG. 25). Here, if the voltage gain of the first inverter 6 is -Gf (Gf&gt;1), the amount of change in the output voltage of the first inverter 6 (i.e., .DELTA.Vof) is: EQU .DELTA.Vof=-Gf (Vref-Vin) (4)
Also, in the second inverter 12, the input voltage is amplified through the same operation. If the voltage gain of the second inverter 12 is -Gs (Gs&gt;1), .DELTA.Vos (i.e., the amount of change of the output voltage of the second inverter 12 from Va) is obtained by multiplying .DELTA.Vof by (-Gs). .DELTA.Vos can be expressed by: EQU .DELTA.Vos=GfGs (Vref-Vin) (5)
Since the formula (5) shows that .DELTA.Vos is proportional to (Vref-Vin), and the coefficient of proportion is GfGs, this proves that the difference between Vref and sampled Vin is output after being multiplied by GfGs. The output voltage of the second inverter 12 is further inverted and amplified to a logical voltage which indicates a comparison result.
An ADC that employs the above-described inverter chopper comparator is described. FIG. 26 shows the layout of a conventional parallel-type 3-bit ADC. A series of reference resistors 4 is connected between first and second reference voltage sources 2 and 3. A comparator array 15 contains seven comparators 14. One input terminal of each comparator 14 is connected to the series of reference resistors 4, the other input terminal thereof is connected to an analog input signal source 1, and its output terminal is connected to a logic circuit 5. The output of the logic circuit 5 is an ADC output 9. Potential differences between the input terminals of the comparators 14, connected to the reference resistors 4, are set equal. In other words, for the reference voltages VRi (i=1, 2, 3 . . . 7) which are obtained from the reference resistors 4, VRi+1-VRi (i=1, 2, 3 . . . 6) are set equal to each other.
The operation of the ADC, shown in FIG. 26, is described by referring to FIGS. 27 and 28. An analog input signal which varies with the lapse of time is sampled by the respective comparators 14 at equal time intervals. In FIG. 27, the abscissa indicates the time, and the ordinate indicates the analog input voltage. ANj (j=-1, 0, 1, 2 . . . , 7) represents the respective sampled analog input voltages at Tsj, where Tsj+1-Tsj (j=-1, 0, 1, 2 . . . . 6) are equal to each other.
The sampled analog input voltage ANj is compared with the reference voltages VRi by the respective comparators 14. For example, if ANj satisfies the condition of VR5&gt;ANj&gt;VR4, the comparators, to which VR7, VR6, and VR5 are applied, each give a level "1" output (i.e., a higher logical level output), from the judgment that ANj is lower than the respective reference voltages VRi. On the other hand, the remaining comparators, to which VR4, VR3, VR2, and VR1 are applied, each give a level "0" output (i.e., a lower logical level output), from the judgment that ANJ is greater than the respective reference voltages VNi. Thus a bit string [1110000] is fed from the comparator array 15. Such a bit string undergoes a code-conversion in the logic circuit 5 and [100] is obtained as the ADC output 9 (see FIG. 28). The output of the ADC varies, depending on the reference voltages VRi each of which serves as a threshold. FIG. 28 shows the relation of the analog input voltage versus the output of the ADC.
The organization of a typical differential chopper comparator is now described. FIG. 29 shows the layout of a conventional differential chopper comparator. Here, the first, second, and third switches are indicated by SWS, SW6, and SW8, respectively. Of them, the third switch, SW 8 is of a 3-terminal type so that it has two input terminals "a" and "b" for receiving two voltage signals to be selected, and a single output terminal "c" for outputting a single selected signal. The comparator is further provided with SW7.
An analog input signal source 1 is connected to the input terminal "a" of SW8 as well as to one terminal of SW5. The other terminal of SW5 is connected to one terminal of one of a pair of input capacitors C5 as well as to the input terminal of a first source follower 19. The input terminal "b" of SW8 is connected to a series of reference resistors 4 that divides a potential difference between voltage sources 2 and 3. One terminal of SW6 is connected to the output terminal "c" of SW8, while on the other hand the other terminal of SW6 is connected to one terminal of the other input capacitor C5 as well as to the input terminal of a second source follower 21. The other terminals of C5 are connected to respective constant-potential points. The output terminal of the first source follower 19 is connected to the non-inverting input terminal of a first differential amplifier 20. The output terminal of the second source follower 21 is connected to the inverting input terminal of the first differential amplifier 20. The inverting output terminal of the first differential amplifier 20 is connected, through one of a pair of coupling capacitors C6, to the non-inverting input terminal of a second differential amplifier 22, while on the other hand the non-inverting output terminal of the first differential amplifier 20 is connected, through the other coupling capacitor C6, to the inverting input terminal of the second differential amplifier 22. The inverting output terminal of the second differential amplifier 22 is connected, through one of the switches SW7, to the non-inverting input terminal of the second differential amplifier 22, while on the other hand the non-inverting output terminal of the second differential amplifier 22 is connected, through the other SW7, to the inverting input terminal of the second differential amplifier 22. FIG. 30, comprised of 30(a) and 30(b), shows the organization of the first differential amplifier 20 along with that of the second differential amplifier 22.
FIG. 31 is the on/off timing diagram of SWS, SW6, SW8 and SW7.
During the sampling period, SW5, SW6, and each SW7 are all in on-state and SW8 is on selection of an analog input voltage Vin from the analog input signal source 1 in which condition each C5 stores the analog input voltage of Vin. Each C6 stores a DC offset voltage between the first and second differential amplifiers 20 and 22. During the holding period, SW5 and SW6 are turned off. During the first comparison period, SW5 and each SW7 are turned off, SW6 is turned on, and SW8 selects a reference voltage Vref from the reference resistors 4, resulting in one of C5's, connected to the input terminal of the second source follower 21, storing the reference voltage Vref. Then during the second comparison period, SW5, SW6, and both SW7 make a transition to off-state, so that a differential voltage between Vin sampled and Vref is amplified by the first and second differential amplifiers 20 and 22, which is output as a voltage comparison result.
As mentioned above, the configuration of four switches SW1, SW2, SW3, and SW4 of the inverter chopper comparator of FIG. 20 is selected frown among those, namely, an NMOS transfer gate, a PMOS transfer gate, and a CMOS transfer gate. These transfer gates are composed of MOS transistors, the conduction between drain and source electrodes of which is controlled with a clock signal (hereinafter referred to as the "switch control signal") delivered to respective gate electrodes. The injection of electric charge into a drain (or a source) region of the MOS transistor through a gate-to-drain (or a gate-to-source) capacitance (hereinafter called "feedthrough") occurs, when the switch control signal makes a transition from HIGH to LOW, or vice versa. This is one of inevitable behaviors of transfer gates. The inverter chopper comparator, as described above, holds the analog input voltage Vin at the time when a transition from the sampling period to the holding period is made. Particularly, in FIG. 20, if electric charge is injected into (or extracted from) the joining point of the first coupling capacitor C1 and the first inverter 6 and injected into (or extracted from) the joining point of the second coupling capacitor C3 and the second inverter 12 when SW1, SW3, and SW4 each make a transition to off-state, this causes errors in the voltage held in the comparator. It is known that the amount of injected (or extracted) electric charge, due to the feed-through, depends upon values of drain or source, gate length, gate width, and threshold voltage (hereinafter these values are called the "device parameters").
FIG. 26 shows one of high-speed ADC architectures which is provided with plural comparators. If the voltage held in each comparator is made varied because of the variation in electric charge injected into the comparators, this presents some problems that the differential nonlinearity error (hereinafter referred to as "DNL") of ADC becomes serious and its frequency characteristics are subject to degradation. Particularly, in a case where the ADC is applied for image processing, DNL is regarded as the important index of image degradation at the time when digital signals obtained are reproduced in the form of image. DNL depends upon the quality of adjustment between comparators. The variation in the device parameters of a MOS transistor has been a major factor determining the yield of the ADC, its costs, and the limit of conversion accuracy.
The mutual conductance variation, due to the variation in the device parameters of the inverters 6 and 12 of each comparator, makes the time constant of charging/discharging of coupling capacitors C1 and C3 vary. This produces a problem that DNL at a high-frequency analog input signal greatly increases. Noise superposed on power supply lines and noise from the logic circuit will get into the comparators. This makes DNL greatly increase. This also results in the degradation in signal-to-noise ratio (S/N).
In accordance with the differential chopper comparator, shown in FIG. 29, electric charge, due to the feedthrough occurring at the time when SW5 and SW6 each make a transition from on-state to off-state, is substantially equally injected into the pair of input capacitors C5 respectively if the difference between Vin (the analog input voltage) and Vref (the reference voltage) is small. Further, such injected electric charge as a result of the feedthrough is deadened in the first differential amplifier 20. Accordingly, the offset error of the threshold voltage is more eliminated as compared to the foregoing inverter chopper comparator. However, if the device parameters of both SW5 and SW6 and the capacitances of C5 vary, the above-described ill effects will appear. This also presents a problem that DNL becomes greater.